1. Field of the Invention
The present invention relates to a technique of achieving low power consumption of a semiconductor integrated circuit by controlling power.
2. Description of the Related Art
Conventionally, it is known to use a Zigzag Super Cut-off CMOS (ZSCCMOS) circuit or a Zigzag Boosted Gate MOS (ZBGMOS) circuit in order to achieve low power consumption of a semiconductor integrated circuit.
FIG. 8 shows a circuit configuration of a ZSCCMOS circuit. As shown in FIG. 8, the ZSCCMOS circuit includes a combinational circuit 50 for which power supply is to be cut off. In the combinational circuit 50, a high potential-side power supply end of a logic gate circuit which outputs “L” immediately before cut-off of power supply is connected to a pseudo-power supply line VDDV connected via a power control transistor MP to a high potential power supply line VDD, while a low potential-side power supply end thereof is connected to a low potential power supply line VSS. A high potential-side power supply end of a logic gate circuit which outputs “H” immediately before cut-off of power supply is connected to the high potential power supply line VDD, while a low potential-side power supply end thereof is connected to another pseudo-power supply line VSSV connected via a power control transistor MN to the low potential power supply line VSS.
With this circuit configuration, the gate-drain voltage of the power control transistor can be maintained low, and a state of the combinational circuit 50 during restoration of power supply can be quickly settled (see Kyeong-sik Min et. al, “Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-Gating Scheme in Leakage Dominant Era”, 2003 IEEE International Solid-State Circuits Conference, session 22, TD: Embedded Technologies, Paper 22.8 (hereinafter referred to as Non-Patent Document 1)).
However, the above-described low power consumption circuit technique has the following problems.
In order to achieve the circuit configuration as shown in FIG. 8, the output of each logic gate in the combinational circuit 50 needs to be settled as “H” or “L” immediately before cut-off of power supply which turns off the power control transistor. Therefore, Non-Patent Document 1 describes a circuit configuration as shown in FIG. 9 which is a flip-flop circuit which supplies an output to the combinational circuit 50. In the circuit configuration of FIG. 9, an asynchronous reset signal or set signal is externally input so that the output of the flip-flop circuit can be forcedly fixed to “L” or “H”. However, in the circuit configuration of FIG. 9, the flip-flop circuit is set into the initial state immediately before cut-off of power supply which turns off the power control transistor. Therefore, the flip-flop circuit cannot continue to hold data which was held. Therefore, when power supply is restored, the state of the combinational circuit 50 cannot be put back to a state as it was before cut-off of power supply, but is invariably initialized.
Non-Patent Document 1 also describes a circuit configuration as shown in FIG. 10. In the circuit configuration of FIG. 10, data is held at the Q output (slave latch circuit) of a flip-flop circuit. Specifically, a clocked inverter G102 and an inverter G103 each comprise a high-threshold voltage MOS transistor. Power supply ends of each inverter are connected to the high potential power supply line VDD and the low potential power supply line VSS, respectively, so that data can be held even when the power control transistor is turned off. In a clocked inverter G101, a power control transistor is inserted between each power supply end and the power supply so that the output of a master latch circuit is cut off when the power control transistor is turned off.
However, in the configuration of FIG. 10, since the Q-output data is held, the output of the flip-flop circuit can be either “H” or “L”. In other words, the output of the flip-flop circuit when power supply is cut off, is not invariably “H” or “L”. Therefore, the output of each logic gate circuit in the combinational circuit 50 cannot be uniquely fixed, so that, during circuit design, it cannot be determined whether the power supply end of each logic gate circuit should be connected to the power supply line or the pseudo-power supply line, which is a serious problem.